Description

Amazon Leo is Amazon’s low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity.

Come work at Amazon!

We're hiring a Sr. RTL Design Engineer – Wireless Modem within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary IP’s.

The Role:
Be part of Amazon Leo’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a innovative wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and compute solutions in latest CMOS generation technologies.

In this role you will:
• Implement system architecture in silicon from system specification to chip specification to RTL to optimizing timing/power to chip level validation.
• Develop solutions optimizing customer experience (throughput, latency, and availability) while meeting power and cost constraints.
• Drive high quality designs for first-time right silicon solutions, and meeting the power objectives through synthesis optimization and power analysis using industry-leading tools (RTLA, PTPX).
• Perform static timing analysis (STA) and timing closure, ensuring designs meet timing constraints across all operating conditions.
• Develop and implement UPF (Unified Power Format) specifications for power intent and multi-voltage domain designs.
• Create standalone verification test bench to verify the correctness of your block. · Work with the verification team and participate in System level verification using test benches constructed using UVM, System C and DPI-C.
• Ensure that the block meets DFT, timing and power targets by working closely with the implementation team.


Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.


Key job responsibilities
• Engage with architects and system engineers to drive hardware micro-architecture.
• Lead design of 1 or more complex data path modules in System Verilog.
• Drive synthesis and physical implementation, working closely with backend teams to achieve timing closure and power targets.
• Perform power analysis using RTLA, PTPX, or other industry-leading tools to optimize power consumption.
• Develop and maintain UPF specifications for power management and multi-voltage domain designs.
• Conduct static timing analysis (STA) and resolve timing violations across multiple clock domains.
• Involve in control plane logic design and interfaces to bus fabrics.
• Explore and propose innovative ideas and work towards optimization of the design.
• Mentor and assign work to junior team members.