Description

Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.

Key job responsibilities
Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes

Drive Optimizations in CAD flows/methodologies for PPA and TAT improvements

Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability.

Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.

Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies.

Be able to independently troubleshoot digital tool flow usage and deploy solutions;

Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments

Create Dashboard and Central reports for project tracking and visualizing QoR/stats