Description

As a Principal Engineer on the Annapurna Labs analog/mixed-signal design team, you will be the technical authority for analog IP that powers AWS's custom silicon portfolio. You will architect, design, and deliver high-performance analog IP blocks — including high-speed SerDes/PHY, PLLs, data converters, power management circuits, and I/O interfaces — across advanced CMOS nodes for products like Graviton, Nitro and Trainium. You will drive IP reuse and portability strategies, lead silicon bring-up campaigns, and set the technical direction for the analog IP roadmap.

Key job responsibilities
•Drive execution: Lead the full design cycle from architecture through silicon validation — spec, schematic, layout, simulation, tapeout, and bring-up.
•Collaborate cross-functionally: Partner with SoC architecture, digital design, physical design, DFT, packaging, and system teams to integrate analog IP seamlessly.
•Set technical direction: Define design methodologies, flows, and best practices. Evaluate and select EDA tools, PDKs, and foundry processes.
•Innovate at scale: Develop IP that is reusable, portable across process nodes, and designed to meet the performance, power, and area (PPA) needs of multiple products simultaneously.