SoC Design Integration Engineer
Apple
Design
Irvine, CA, USA
USD 171,600-302,200 / year + Equity
Posted on Dec 20, 2025
We’re looking for individuals who relish a good challenge and are dedicated to overcoming limits. You'll be at the heart of chip design! Apple recently announced first in-house cellular modem platforms, the C1 and C1X, designed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Apple’s custom silicon. You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and you’ll help us innovate new cellular technologies that continually outperform the previous iterations! Do you want to have an impact on every single Apple product? As a member of Cellular SoC design team, you will be at the center of a SoC design and integration at the leading process technology node with a critical impact on getting functional products to millions of customers. You will work on cutting-edge technologies and collaborate with cross-functional teams to deliver groundbreaking solutions.
As a SoC Integration Engineer, you will have responsibilities to design and integrate IPs. • Working with other specialists that are members of the SoC Design, SoC Design Verification, System Verification, STA, and Physical Design teams to implement designs/flows for sophisticated SoCs. • Integrating various IPs and ensuring design meets DFT (design-for-test), CDC (clock domain crossing), Synthesis/Static Timing and Power Requirements. • Developing micro-architecture and design specifications. • Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability and improve front-end design methodologies. • Implementing and verifying sophisticated logic designs. • Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases; from concept to silicon bring-up.
- IP Integration: Integrate third-party or internal IP blocks (e.g., CPU, memory controllers, custom logic, Mixed Signal/Analog IOs) into a SoC.
- RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB) are correctly implemented.
- Top-Level Assembly: Create and maintain top-level SoC RTL, wrappers, and interconnects.
- Explore the use of AI/ML tools to improve SoC Design and Integration.
- Linting and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis to ensure design quality.
- Timing Closure: Work closely with physical design and STA teams to achieve timing closure at top level.
- Functional Verification Support: Provide integration-level support to design verification teams, including simulation bring-up and debug.
- Documentation and Reviews: Create and maintain design documents and participate in design reviews.
- BS and 10+ years of relevant industry experience.
- Solid understanding of digital logic design and RTL development (SystemVerilog, Verilog).
- Knowledge of low-power design techniques and power optimization strategies.
- Attention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs.
- Knowledge of ASIC tool flows: lint, synthesis, CDC, RDC, DFT, STA.
- Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence).
- Experience with bus protocols (AXI, AHB, APB) and interface standards (PCIe, USB, DDR, SPI, SPMI, I2C, I3C, etc.).
- Decent scripting skills (Python, Perl, TCL, Shell) for automation.
- Good debugging and problem-solving skills.
- Excellent communication and cross-functional collaboration.
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