Memory Performance Engineer, Platform Architecture
Apple
IT
Santa Clara, CA, USA
USD 147,400-220,900 / year + Equity
Posted on Jan 8, 2026
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! In this role, you will be a member of the Platform Architecture team, working with hardware and software engineering groups to shape the architecture of Apple's future System-on-Chips (SoC). We are seeking an energetic and highly motivated SoC performance engineer to drive development of our memory controllers and system caches for the next-generation of AR/VR and Cellular/5G applications. The position calls for independent performance modeling and simulation, documentation, and collaboration with design/software teams. We are looking for SoC engineers with a passion to innovative new hardware concepts and model them in C++/Python to demonstrate their value and impact.
You will have responsibilities for developing the SoC level solutions that drive the architecture of Apple’s future System-on-Chips. Your work will be highly visible and critical to delivering the best performance and power efficiency in Apple’s future products. You will be expected to collaborate with all the hardware and software teams that are part of Apple’s SoC development: C++ performance modeling of proposed architectural solutions and features. Writing architectural specification documents in collaboration with engineers across different disciplines. Gathering, analyzing, and validating measured and simulated results to compare architectural design alternatives. Working with the multi-functional teams to develop architectural solutions. Improving Apple’s modeling platform by developing APIs, tools, and optimal standard examples that can be used throughout the company. Carefully analyzing and presenting results to enable data specific architecture/design. Measuring and analyzing existing SOC and workloads. Some international travel is required for this position
- BS and a minimum of 3 years relevant industry experience
- Solid knowledge of cache management and memory controller for DRAM technologies. Prior experience on writing a cache and memory simulator using C++ is a big plus.
- Excellent C/C++/scripting coding, debug, and testing skills.
- Papers published in top computer architecture conferences/journals and filed patents related to computer architecture, demonstrating ability of designing and evaluating different cache and memory performance techniques
- Prior work on analyzing the memory access patterns and bandwidth/latency requirements of CPU, GPU, Video, Camera, Machine Learning hardware accelerators or similar areas.
- Expertise in cooperative code development using a revision control system such as GIT.
- Strong communication and documentation skills.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.