Gate-level SigEM/SEB/FIT CAD Engineer
Apple
San Francisco, CA, USA · Oregon, USA · San Francisco Bay Area, CA, USA · Multiple locations
USD 147,400-272,100 / year + Equity
Posted on Feb 26, 2026
Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it! As a key member of our best-in-class CAD Group, you will be part of building innovative designs. We will apply your hands-on experience in electromigration (EM), static error band (SEB), failure in time (FIT), self-heating effect (SHE), and thermal analysis to develop, define, and refine the methodologies and flows for gate-level as well as transistor-level designs. Major tasks will include IP / SOC signal EM analysis for clock and data nets, SOC FIT budget validation, power-grid EM verification, 3DIC and interposer thermal integrity, power switch and standard cell EM/SHE characterization, design abstract and reuse, sign-off, and ECO, and much more. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products?
In this highly visible role, your primary responsibilities will include: • Contribute to the development and deployment of comprehensive EM/SEB/thermal methodologies across multiple advanced node designs • Develop and implement customized EM/SEB/thermal solutions which scale with accuracy and capacity challenges, following established best practices and design guidelines • Support and maintain the EM/SEB/thermal flow from concept through sign-off, including automation, quality metrics, and continuous improvement • Collaborate with and support various teams (Physical design and Integration, Clock and Signal integrity, Circuit design, Power, Package, System, Technology) on EM/FIT requirements and trade-offs • Develop, validate, and maintain EM/thermal rule decks and verification methodologies for clock trees, high-speed data paths, and critical signal nets across multiple projects • Work closely with EDA vendors and foundries for tool qualification, model development, enhancement requests, and roadmap alignment • Participate in correlation studies between EM analysis tools and silicon failure analysis data, contributing to methodology improvements based on findings
- Experience with EM/SEB/FIT/SHE/Thermal methodologies and calculations
- Minimum BS + 3 years of relevant industry experience
- Understanding of current density calculations, heating effects, and electromigration failure mechanisms
- Experience in some of the analysis involved in EM - extraction, timing, simulation, EM modeling, physical design, and physical verification
- Experience in EDA tools and CAD flow development
- Proficiency in at least one of Tcl, Python, or Perl scripting languages
- Exposure to or knowledge of industry leading EMIR tools e.g. Voltus, Voltus-Fi, RedHawk-SC, Totem
- Experience with analysis, optimization, or debugging of IR/IVD/EM issues on high performance, large-scale designs and silicon
- Familiarity with advanced packaging technologies (2.5D/3D/3.5DIC) and their unique EM challenges
- Interest in AI/ML-driven innovation for CAD workflows
- Experience in development of software in multi-user, multi-site environments
- Ability to coordinate and drive initiatives with appropriate guidance
- Strong communication and presentation skills
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.