Memory Packaging Engineer
Apple
Santa Clara, CA, USA
USD 181,100-318,400 / year + Equity
Posted on May 1, 2026
Join the team at the heart of memory innovation for every Apple product. As a Memory Packaging Engineer, you will architect the memory solutions that power the industry-leading performance of Apple's hardware. We push the boundaries of bandwidth density, power efficiency, and system integration through meticulous co-design between memory technology and our world-class systems. If you are driven to solve the industry's toughest packaging challenges, your work will have a profound and lasting impact on the products used by millions.
In this role, you will drive the definition, development, and qualification of next-generation memory packages critical to Apple’s future products. You will guide the package roadmaps of our memory partners and collaborate with internal engineering teams to enable bandwidth and density scaling. Your ownership will span the entire product lifecycle, from initial concept through qualification.
- Determine the direction of next-generation package architecture by evaluating available and emerging packaging technologies.
- Collaborate with cross-functional teams to solve integration challenges, including electrical, mechanical, and thermal.
- Drive vendor DOEs and failure analysis to improve downstream yield and maintain world-class quality and reliability.
- Define the memory package POR (plan of record): Package form factor, process, layout, stackup, and bill of materials (BOM).
- Drive memory vendors to develop package materials and technology for leading-edge package design rules.
- BS and 10+ years of relevant industry experience
- MS or PhD preferred, with 10+ years of industry experience in package design and assembly process development of high-bandwidth and high-density memory packages.
- Strong knowledge of thin-die stacking technologies including wirebond, flip-chip, and wafer/die bonding.
- Strong knowledge of packaging materials and design to engineer warpage and CTE properties and mitigate thermal challenges.
- Solid working experience in package test and reliability, system-level downstream process interaction, and packaging inspection metrology.
- Deep understanding of SI/PI co-design with memory die and high-speed DDR or differential signaling.
- Understanding of how memory die floorplan and architecture influence package structure and routing, with experience collaborating with memory die design teams.
- Excellent communication skills for collaborating with internal teams and managing external vendors.