Senior Design Verification Engineer, Silicon
Senior Design Verification Engineer, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
- Experience verifying digital logic at RTL level using SystemVerilog or C/C++.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation.
- Experience with building verification methodologies that span simulation, emulation, and FPGA prototypes.
- Experience in one or more of the following: Operating Systems, Memory Management, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, or Packet Processors.
- Experience with Interconnect Protocols.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities
- Plan and execute the verification of the next generation configurable interconnect, memory management, power controller, and chips pervasive IP.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
- Develop cross-language tools and scalable verification methodologies.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
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