ASIC RTL Design Engineer, Machine Learning Accelerators
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- 2 years of experience in Digital design using SystemVerilog RTL.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science.
- 4 years of experience in digital/ASIC design using SystemVerilog or RTL.
- Experience in one or more successful ASIC products from concept to silicon.
- Experience interacting with software, system hardware, and other cross-functional teams.
- Experience defining SoC IP interfaces and methodologies.
- Understanding in computer architecture/memory subsystem architecture.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing cutting-edge ASICs used to accelerate Machine Learning computation in Google's data centers. You will participate in the microarchitecture, design, documentation, and implementation of the next generation of Machine Learning center accelerators.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Work independently and collaboratively to create and review ASIC/SoC subsystem design architecture and microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines.
- Work with Design Validation (DV) teams to create testplans for, verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
This job is no longer accepting applications
See open jobs at Google.See open jobs similar to "ASIC RTL Design Engineer, Machine Learning Accelerators" AnitaB.org.