Full Chip Layout Physical Design Engineer
Full Chip Layout Physical Design Engineer
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience with physical design flows and methodologies (RTL2GDS).
- Experience with semiconductor process technologies (deep submicron, advanced nodes like 5nm and below), and device physics (MOSFET/FINFET).
- Experience with Design For Testability (DFT) and low-power design methodologies.
- Experience with UPF (Unified Power Format) and its application in physical design.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
- Experience with scripting languages such as Perl, Python, or Tcl.
- Excellent analysis skills, with the ability to understand, debug, and resolve issues in the design flow.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Develop and optimize the overall layout of the chip, including partitioning, macro and IP placement, and pin placement.
- Design and implement efficient power delivery networks power grids to ensure stable power to all parts of the chip.
- Develop and validate high-performance, low-power clock networks (e.g., Clock Tree Synthesis (CTS)) to ensure proper synchronization across the entire chip.
- Develop, enhance, and maintain custom scripts (e.g., Tcl, Perl, Python) for automation and improved efficiency.
- Conduct extensive Design Rule Checks (DRC) to ensure the layout adheres to manufacturing rules, performing Layout Versus Schematic (LVS) checks to verify that the physical layout matches the logical design.
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