Senior Hardware Signal & Power Integrity Engineer
Microsoft
Senior Hardware Signal & Power Integrity Engineer
Santa Clara, California, United States
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Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.
The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives
Central to our mission is development of platforms for Azure Datacenters based on our highly programmable data processing chip (DPU). As a Hardware Signal & Power Integrity Engineer, you will be responsible for ensuring the design meets electrical specifications, adhere to standards compliance and possess good margins.
Qualifications
Required Qualifications:
- Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience
- OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience
- OR equivalent experience.
- 3+ years experience in SI & PI analysis of complex multilayer PCBs & backplanes
- 3+ years experience in simulation/correlation using 2D/2.5D/3D simulation tools.
- 3+ years experience using Keysight ADS, Ansys HFSS, Cadence Sigrity, PowerSI, Ansys SIwave, Hspice, Matlab
- 3+ years of technical knowledge & working experience with PCIe, DDR4/DDR5 (Memory, PHY, Controller), Ethernet (MAC/PHY), NRZ & PAM4 Serdes, I2C, SPI, MDIO..Etc
- 3+ years of hands-on experience in using lab/debug tools (e.g., High-speed Oscilloscopes, TDR, VNA, Bertscope, and Spectrum Analyzer)
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
- 11+ years technical engineering experience
- OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
- Experience in bring-up/debug/characterize high speed serial links - DFE Tuning, Monitoring Eye quality, BER..Etc
- Knowledge with scripting (PERL, TCL, etc)
- Knowledge on package level simulation
Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: US corporate pay information | Microsoft Careers
Microsoft will accept applications for the role until Nov 17th 2025.
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#SCHIE
#azurehwjobs
Responsibilities
- Perform system level signal integrity simulations of high-speed interfaces, create simulation models and develop simulation methodology for the designs.
- Perform power integrity simulations including AC and DC analysis.
- Develop serdes channel simulation models and correlate to test structures.
- Support stackup creation, develop layout/SI checklists, work with board engineers and layout designers to implement all SI rules.
- Perform SI DVT measurements on boards and correlate measurements with simulation results.
- Work cross-functionally with the other teams to plan and design the SI/PI needs for the system.