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Showing 28 jobs
CPU Post Silicon Power and Performance Engineer (Sr Engineer - Staff)
CPU Post Silicon Power and Performance Engineer (Sr Engineer - Staff)
Austin, TX, USA
USD 148,300-222,500 / year + Equity
1 month
Telecommunication
5001+ employees
IPO
Senior
CPU Post Silicon Power and Performance Engineer (Sr Staff-Principal)
CPU Post Silicon Power and Performance Engineer (Sr Staff-Principal)
Austin, TX, USA
USD 179k-268,400 / year + Equity
1 month
Telecommunication
5001+ employees
IPO
Senior
Senior Staff GPU Validation and Emulation Engineer
Senior Staff GPU Validation and Emulation Engineer
San Diego, CA, USA
USD 195,200-292,800 / year + Equity
3 days
Telecommunication
5001+ employees
IPO
Senior
Staff Systems Performance Engineer
Staff Systems Performance Engineer
San Diego, CA, USA
USD 148,300-222,500 / year + Equity
3 days
Telecommunication
5001+ employees
IPO
Mid-Senior Level
Silicon Engineer, Digital Design, Quantum AI
Silicon Engineer, Digital Design, Quantum AI
Mountain View, CA, USA
USD 156k-229k / year + Equity
7 days
Internet Services
5001+ employees
Mid-Senior Level
Sr. Staff CPU Physical Design CAD Engineer
Sr. Staff CPU Physical Design CAD Engineer
Santa Clara, CA, USA
USD 198,700-298,100 / year + Equity
25 days
Telecommunication
5001+ employees
IPO
Senior
Sr.Engineer/Staff EMIR CAD Engineer
Sr.Engineer/Staff EMIR CAD Engineer
Santa Clara, CA, USA
USD 167,100-250,700 / year + Equity
1 month
Telecommunication
5001+ employees
IPO
Senior
CPU Physical Design Pathfinding Engineer
CPU Physical Design Pathfinding Engineer
San Diego, CA, USA
USD 211,900-317,900 / year + Equity
1 month
Telecommunication
5001+ employees
IPO
Senior
Systems Performance Lead
Systems Performance Lead
San Diego, CA, USA
USD 218,300-327,500 / year + Equity
1 month
Telecommunication
5001+ employees
IPO
Director
CPU Physical design Engineer
CPU Physical design Engineer
Austin, TX, USA
USD 148,300-222,500 / year + Equity
1 month
Telecommunication
5001+ employees
IPO
Mid-Senior Level
Principal CPU Systems Debug Architecture/RTL Engineer
Principal CPU Systems Debug Architecture/RTL Engineer
Santa Clara, CA, USA
USD 233k-349,600 / year + Equity
1 month
Telecommunication
5001+ employees
IPO
Senior
Silicon Validation Engineer
Silicon Validation Engineer
San Diego, CA, USA
USD 133,600-200,400 / year + Equity
1 month
Telecommunication
5001+ employees
IPO
Mid-Senior Level
Sr. Staff CPU Physical Design CAD Engineer
Sr. Staff CPU Physical Design CAD Engineer
Santa Clara, CA, USA
USD 198,700-298,100 / year + Equity
1 month
Telecommunication
5001+ employees
IPO
Senior
DV CAD Engineer
DV CAD Engineer
Santa Clara, CA, USA
USD 198,700-298,100 / year + Equity
1 month
Telecommunication
5001+ employees
IPO
Mid-Senior Level