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Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Location: Santa Clara, CA, USA; Hillsboro, OR, USA
Compensation:

USD 136k-264,500 / year + Equity

Posted:
15 days
Senior
Cables
Communications Equipment
Connectivity
Connectivity Products
Electronic Equipment and Instruments
Ethernet
Hardware
Infrastructure
Low Latency
Networking
Routers & Switches
Science and Engineering
Semiconductors
Semiconductors & Related Devices
Software
Technology
Technology and Computing